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Procedure

Follow the instructions on how to get, compile and run gem5. Run the mcf_r benchmark and try to understand how the simulator works from this experience. Read through the gem5 script source code because later you will need to run the same benchmark from your custom script.

Environment Variables

The provided script requires setting the GEM_PATH, GEM_CONFIGS, and GEM_SRC environment variables

  • Copy scripts/SiFiveP550/* to your favorite directory and figure out how to run SPEC CPU2017 benchmarks

    tip

    Look at the program arguments

    note

    There are a number of different files provided, they divide the cache, functional unit and interconnect behaviours for the simulated processor. You may have to modify these files as well.

  • Rename the script to SiFiveP650.py, and alter it to reflect the following parameters (some parameters may already match this specification):

    • An Out-of-Order CPU capable of fetching, decoding, issuing, and dispatching 3 instructions per cycle
    • The CPU must have the following functional units:
      • 2 integer ALUs
      • 1 integer multiplier
      • 1 integer divider
      • 1 memory read/write port
    • Separate 32KB, four-way set-associative L1 caches for instructions and data with 64-byte cache lines
    • An 8MB, direct-mapped L2 unified (private) cache with 64-byte cache lines

  • Run a simulation of the mcf_r benchmark using your SiFiveP650.py script.

    • The simulation should run for 100 million instructions.
tip

It is possible to hard-code the script to match the assignment specifications but it is better to learn to use command-line arguments. Using pre-existing command-line arguments and adding new ones will prove useful in this and future assignments and improve overall productivity.

This lab exercise was created by Taylor Lloyd for Dr. J Nelson Amaral, with inspiration from lab exercises created by Jean-Loup Baer and his team at the University of Washington. It was refactored by Rodolfo Wottrich in April/2016 based on student feedback and modified in 2024 to reflect the course change to the RISC-V ISA by Ayrton Chilibeck.