The Standard Library

The gem5 standard library is a collection of pre-built and pre-configured modules that you can drop into a gem5 'System'. the goal is to make it easier to start simulating and spend less time building that ~200 line configuration file that you built in the basic examples.

You can find all of the code for the standard library in the following folder:

$GEM_PATH
├── ...
├── configs
├── include
├── src/
│   ├── arch
│   ├── base
│   ├── ...
│   └── python/
│       ├── gem5
│       ├── m5
│       └── pybind11
├── system
├── tests
└── util

You will more than likely need to refer to the code in order to make a working example, or you can try to get your LSP to index this folder by adding it to the $PYTHONPATH of your system.

Components of the Standard Library

If you cd into the gem5/components directory you will see the following structure:

.
├── boards
├── cachehierarchies
├── devices
├── memory
└── processors

The fundamental abstraction the standard library relies on is the concept of a System. A system is capable of executing code, and will normally consist of a processor and its memory systems. In gem5, when using the standard library, it is easiest to create a system first using a board. A board is much like a motherboard if you were to build your own computer. You can take and 'plug in' whichever hardware you want to use, normally this consists of a processor and its associated cache hierarchy and memory.

Using the gem5 standard library, our configuration file goes from the behemoth of the basic implementations, to the following:

from gem5.components.boards.simple_board import SimpleBoard
from gem5.components.memory import SingleChannelDDR3_1600
from gem5.components.processors.cpu_types import CPUTypes
from gem5.components.processors.simple_processor import SimpleProcessor
from gem5.components.cachehierarchies.classic.private_l1_cache_hierarchy import PrivateL1CacheHierarchy
from gem5.isas import ISA
from gem5.resources.resource import obtain_resource
from gem5.simulate.simulator import Simulator
from gem5.utils.requires import requires

from m5.objects import *

# Ensure the gem5 binary is compiled to the RISCV ISA target
requires(isa_required=ISA.RISCV)

cache_hierarchy = PrivateL1CacheHierarchy(l1d_size="32KiB", l1i_size="32KiB")

memory = SingleChannelDDR3_1600(size="8GiB")

processor = SimpleProcessor(
    cpu_type=CPUTypes.O3,
    num_cores=1,
    isa=ISA.RISCV,
)

board = SimpleBoard(
    clk_freq="3GHz",
    processor=processor,
    memory=memory,
    cache_hierarchy=cache_hierarchy,
)

board.set_se_binary_workload(obtain_resource("riscv-hello", quiet=True))

simulator = Simulator(board=board)
simulator.run()

Components of the Standard Library​

Components of the Standard Library